TL;DR — Huawei’s τ (Tao) Scaling Law, announced at IEEE ISCAS 2026, reframes Moore’s Law: instead of shrinking transistors, optimize a time constant τ across the entire computing stack. The paper is real, the production data is concrete, but the “first scaling law since Dennard” claim deserves scrutiny. This is mostly a solid 3D-integration engineering paper wrapped in a strategic narrative about how China builds high-performance chips without leading-edge lithography.

What Was Announced

On May 25, 2026, at the IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai, He Tingbo — President of Huawei’s Semiconductor Business — delivered a keynote titled “Exploration and Practice of a New Semiconductor Path.” The headline: a new scaling principle Huawei calls τ (Tao) Scaling, marketed as China’s first systematic semiconductor industry law.

The paper, “A Time Scaling Theory for Multi-Layer Electronic Systems,” was simultaneously posted to ChinaXiv as a preprint (ChinaXiv:202605.00224). Within hours it had over 30,000 reads and 13,000 downloads — unusual for a preprint server.

This is worth taking seriously precisely because it’s published, not a marketing deck.

The Core Reframe

For 60 years, Moore’s Law has driven semiconductor progress by shrinking transistor dimensions. The paper opens with the industry consensus:

“For six decades, Moore’s geometric scaling drove progress in semiconductors… returns from pure dimensional shrinking have flattened, leading-edge design budgets exceed one billion dollars per chip, and cost-per-transistor at the most advanced nodes is no longer falling.”

So what’s the successor principle? The paper’s pivot is the key insight:

“Spatial scaling served merely as the instrument for compressing time.”

In other words: Moore’s Law was never really about transistor area — it was about reducing the time it takes for a system to do something. Users don’t care that their chip is 3nm. They care that their app opens in 200ms instead of 300ms.

If time was always the underlying goal, why not measure progress in time directly? That’s τ scaling: a single characteristic time constant τ as the unifying optimization target across the entire computing stack — from picosecond transistor switching to multi-second AI workload latency, spanning twelve orders of magnitude.

The paper’s strongest methodological claim:

“τ scaling is the first scaling principle since Dennard to establish a shared optimization target across the entire computing stack.”

This is a big claim. We’ll revisit it.

How τ Works: Four Layers

The framework decomposes τ into four stack layers, each with its own optimization target:

The interesting move is that the paper treats frequency, latency, bandwidth, throughput as all being governed by τ at their respective layers. One framework, twelve orders of magnitude.

Production Demo #1: Kirin 2026 SoC

This is the most concrete part of the paper. The Kirin 2026 chip — launching this autumn — is the first commercial product using LogicFolding.

What LogicFolding Actually Does

“LogicFolding is a design methodology that partitions digital, analog, and memory circuits across vertically stacked active tiers.”

In plain terms: instead of laying out logic in a single 2D plane, split the design across multiple active silicon layers connected by high-density hybrid bonding. Some signal paths that previously had to traverse long horizontal distances now travel short vertical ones.

The promise:

“Signal wires become substantially shorter, parasitic RC decreases sharply, clock skew tightens, and the chip operates at a higher clock frequency at the same device node.”

Crucially: at the same device node. This isn’t a process shrink. It’s a structural reorganization that recovers performance from the interconnect, not the transistor.

The Numbers (from the paper)

Measured on Kirin 2026:

If these hold up under independent measurement, this is a genuine engineering achievement — not just a process node bump.

Production Demo #2: AI Data Centers

The harder test for any scaling principle: does it work at gigawatt scale?

“Whether a principle developed in the milliwatt smartphone regime survives translation to the gigawatt regime of AI training and inference.”

The paper’s answer: yes, but only if you treat τ as a system-level target, not a per-accelerator optimization.

The Bottleneck Reframe

The paper’s most important industry observation:

“Modern AI systems are dominated by data, not by compute. Over 80% of energy in large AI clusters is spent on data movement, and over 70% of system cost goes to data storage.”

This is the unspoken truth of AI infrastructure: TOPS numbers on chip datasheets are mostly irrelevant when 80% of energy goes to moving bytes between chips, racks, and storage tiers.

Three Solutions

1. Unified Bus (灵衢总线) — A memory-semantic fabric eliminating protocol conversions between PCIe / NVLink / RDMA / Ethernet / InfiniBand layers. The claim:

“Conversion-free, peer-to-peer transmission.”

Measured impact: end-to-end remote access latency from tens of microseconds to ~100ns — a roughly 500× reduction in system τ on the main communication path.

2. Hi-ONE (High-density Optical-interconnect-Node Engine) — Near-package optical I/O. At multi-Tb/s per chip, copper becomes physically impractical:

“At multi-Tb/s per chip, copper becomes physically impractical.”

Hi-ONE delivers 8 Tb/s per module, extends face-to-face distance to 100m, and matches the chip’s UB bandwidth over a single optical link.

3. 3D Folding — The fan-out dilemma: compute scales with chip area (N²), but I/O and power scale with chip perimeter (N). Solution: fold I/O and power into vertical stack instead of crowding the edge.

Projection: more than 100× growth in hardware integration by 2035.

The Honest Caveat

Buried in the paper is one of the most important sentences for understanding what τ scaling is not:

“τ is a time law, not a joule law.”

Translation: τ scaling solves time, not energy. If you make an AI cluster 10× faster but it also draws 10× more power, you’ve just moved the bottleneck from latency to electricity, cooling, and dollars.

The paper acknowledges this and gestures at the obvious complements: protocol overhead reduction, lower per-bit transmission energy, near-memory computing, backside power delivery, dynamic voltage/frequency scaling. But the framework itself doesn’t solve energy. Anyone evaluating τ scaling should remember this.

It’s worth noting that He Tingbo explicitly acknowledges this in the paper — unlike most marketing-driven “new law” announcements, which tend to gloss over their boundaries.

Earned Credit vs. Marketing

What stands up

• Real paper, real data. ISCAS keynote + ChinaXiv preprint with concrete production numbers. Not a slide deck.
• Honest about limits. The “τ is not a joule law” caveat shows genuine engineering humility.
• Strategically sound. Without access to leading-edge EUV lithography, China needs a path to high-performance chips that doesn’t depend on 2nm or 1nm process nodes. 3D integration plus system-level optimization is that path. The framework gives it a name and a measurable target.
• Kirin 2026 ships this autumn. Verifiable claims have a verification date.

What deserves scrutiny

“First scaling principle since Dennard” is a load-bearing claim. But:

• 3D integration has been studied for years. TSMC’s CoWoS, Intel’s Foveros, AMD’s chiplet packaging, Samsung’s X-Cube — these are all forms of vertical integration.
• HBM is essentially a 3D-folded memory stack.
• Imec’s CFET research aims at gate-level 3D folding.

The paper differentiates LogicFolding from existing 3D IC and chiplets by arguing they operate at the packaging layer, while LogicFolding operates at the circuit topology layer inside the chip. That’s a legitimate distinction — but it’s an incremental one, not a paradigm break.

“1.4nm equivalent density by 2031” is a density target, not a process node. The paper is careful about this — but the surrounding press has not been. Equivalent density via 3D stacking is real; it is not the same as fabricating a true 1.4nm node, and shouldn’t be conflated.

“381 chips in 6 years using τ scaling” is post-hoc framing. Huawei has been shipping chips for years; retroactively grouping them under a unified principle is good narrative but doesn’t validate the principle as predictive.

No public benchmarks against the competition. TSMC N2, Intel 18A, Samsung 3GAP — where do they sit on this τ chart? The paper doesn’t say. Until independent measurement compares apples to apples, the “100× by 2035” projection is a roadmap, not a result.

Why This Matters Strategically

Strip the “scaling law” framing and what’s left is a coherent industry argument:

“You don’t need the most advanced lithography to build competitive high-performance chips, if you reorganize circuits in 3D and treat the entire system as a single optimization target.”

This is the technical case for a China-led semiconductor strategy that doesn’t depend on access to ASML’s EUV machines. It’s also a vision for how AI infrastructure could be built differently — interconnect-centric, system-co-designed, optical at the edges rather than copper everywhere.

Whether or not τ scaling becomes “the next Moore’s Law,” it’s a real-world demonstration that the post-Moore era has multiple paths. The question is which path delivers on its claims.

What to Watch

• Kirin 2026 launch (Autumn 2026): Are the 41% efficiency and 55% density gains independently measurable?
• ISCAS 2026 paper full text: Independent review of LogicFolding’s claimed RC reductions vs alternative explanations.
• Industry response: Do TSMC, Intel, Samsung adopt τ-style framing? Or counter with their own “scaling principle” branding?
• Energy data: Since τ doesn’t solve energy, what’s the actual J/op for AI workloads on Huawei’s Ascend silicon vs NVIDIA’s latest?
• Beyond Kirin: Does LogicFolding land in Ascend AI chips next? The paper claims AI-system applicability but the production demo is mobile SoC.

Bottom Line

The τ Scaling paper is a solid engineering paper with an oversized strategic narrative wrapped around it. The technical core — LogicFolding, Unified Bus, Hi-ONE, 3D Folding — is real work with measurable claims. The framing as “the next Moore’s Law” oversells what is, methodologically, an incremental extension of well-known 3D integration techniques combined with system-level co-design.

That’s not a criticism. Most real engineering progress is incremental. The marketing layer is what funds the engineering. What matters is whether the Kirin 2026 ships this autumn with the numbers the paper claims. If it does, China just published a credible technical roadmap for high-performance chips that doesn’t depend on access to leading-edge lithography. That’s a much bigger deal than “the next Moore’s Law.”

References

• Tingbo He — A Time Scaling Theory for Multi-Layer Electronic Systems (ChinaXiv preprint)
• Huawei official announcement — ISCAS 2026 τ scaling
• EEFocus — Deep read of He Tingbo’s “Time Scaling” paper
• Gizmochina — Huawei proposes Tao Law as alternative to Moore’s Law
• 21 Economic Net — What is the Tao Law and how is it different from Moore’s Law